1. Field of the Invention
This invention relates to manufacturing of integrated circuits and more particularly to burn-in.
2. Description of the Related Art
For semiconductor devices, it often takes time for a failure to manifest itself. That is, although the semiconductor device may initially pass all tests, after a short time in the field the device fails. That is commonly referred to as infant mortality. In order to detect such latent defects, the manufacturing process typically employs an approach called burn-in to detect these latent failures. During burn-in the device is operated at elevated temperatures and/or voltages. By operating the device at an elevated temperature and/or voltage, the failure mechanism is accelerated and therefore occurs earlier in time. Tests performed after burn-in can determine whether latent defects uncovered during burn-in are present in the device. Burn-in time is typically measured in hours and is a function of temperature and/or voltage.
The temperature set point during burn-in testing is important because anything below the normal operating temperature specification, e.g., 95° C., does not achieve any acceleration. At a temperature of, e.g., 120° C., one may obtain the desired acceleration factor. At some higher temperature (dependent on package substrate and die size) the C4 bumps on the die start to crack from stress caused by thermal coefficients of expansion (TCE) mismatches in silicon and the package, as well as potentially shortening the overall life of the product. At even higher temperature damage to the device itself can occur. Thus, the window of desired and useful temperatures is relatively small.
Today's semiconductor devices, such as high power microprocessors, have a relatively new problem: a thermal gradient that prevents testing all areas of the die at the required temperature. This gradient occurs because the power can be concentrated in a smaller area and changes more abruptly. That is, the surface of the die is not at a uniform temperature. Therefore, the manufacturing process makes trade-offs between taking longer to burn-in the die or exceeding desired temperature limits.
Note that temperature gradients increase by roughly 50% each time the die is shrunk and the power level held constant. Thus, as semiconductor devices shrink from 130 nm to 90 nm, and then to 65 nm, and 45 nm, the thermal gradient problem will continue to increase. Thus, the problem of thermal gradients is expected to continue to increase.
There are several options for addressing the natural thermal gradient of any high power semiconductor device. The first option is just to run the semiconductor device much longer than is financially or logistically possible. A second option is to ship semiconductor devices of reduced quality by not extending the burn-in times. Obviously, that approach is generally not acceptable. A third option would be to increase the temperature to accelerate the cooler areas, but that could raise the temperature in higher power density areas beyond the safe limits and possibly create new problems in the silicon. Thus, the existence of the thermal gradient can force a choice between a chosen temperature for burn that over-tests some areas of the die or under-tests other areas. Today, with 35° C. gradients and even higher gradients projected for smaller geometry devices, the ability to effectively accelerate failures for all areas of the die is in question.
Thus, it would be desirable to provide improved burn-in for semiconductor devices by addressing the thermal gradient issue.